As semiconductor integrated circuit products become more and more sophisticated, manufacturers continue to look for ways to increase the usefulness of particular circuit designs without having to continually redesign circuits as that have common elements. For example, many times circuit has different circuit elements on a single chip that can be enabled by activating a programmable element, such as a fuse, anti-fuse, programmable read-only memory (PROM), resistive random-access memory (RRAM), magnetic random-access memory (MRAM), or the like.
At she same time, manufacturers are seeking ways to construct packaged integrated circuit products in smaller or more compact packages. One way this has been accomplished is to stack integrated circuit chips, or dies, one on she other, with signals being conducted among the chips by vias in each chip to contact a conductor of the adjacent chip. (The term “via” is used herein to mean a structure having a conductor formed in a substrate through hole, wish conductor portions exposed on each side of the substrate, thereby forming a through connector in the substrate.) Often the vias are in a predetermined pattern so that the via pattern of one chip aligns with the via pattern of an adjacent chip so that when the chips are stacked, electrical connections between the chips are established.
This has led to the development of a three-dimensional approach, including multiple chip or die stacking and wafer stacking. Multiple substrates that include through-silicon-vias, or TSVs, can be stacked on one another to achieve such three dimensional integration. In particular, the TSVs of different substrates can conduct signals from one substrate to another without the use of, for example, wires or other conductors.
Nevertheless, typically, hundreds or thousands of integrated circuits are constructed on a large semiconductor wafer, for example, of 12 inches in diameter. The integrated circuits are patterned into chips which will be cleft from the wafer into individual chips, or dies. Each of the chips on the wafer has a number of bonding pads to which electrical connections to the integrated circuits ultimately will be made. The bonding pads are typically formed on the frontside of the chips (i.e., the side of the chip on which the transistors of the integrated circuit are formed). In many cases, the chips are made larger than they otherwise would be in order to accommodate the large number of bonding pads.
The bonding pads are also used during fabrication for testing of the integrated circuits on the chips and for enabling programming of programmable elements that may be included on she chips. During this time, for example, if a particular circuit is found to be non-functional, the programmable elements may be activated from the frontside bonding pads, for example, by blowing a fuse or activating an antifuse, to remove the nonfunctional circuit or reroute signals around it. Typically, the programming is done during fabrication and testing, before the chips are assembled into a stacked, mounted, or packaged product.
Once a stack of chips is fabricated, it becomes impractical to address programmable elements on the chips. For example, in a stack of identical chips, blowing a fuse on one chip at a particular level will result in fuses in the same location on other chips in the stack being blown. This problem can be addressed using more complex metallization patterns, but it can be seen that the complexity of the overall structure is also significantly increased, and is not done because of the expense of the mask sets used in fabrication.
Moreover, using standard programming techniques, programming signals are limited in the amount of voltage or current that can be applied because the programming is done from pads on the frontside that are not necessarily located in close proximity to the element to be programmed and the programming signals may be conducted through lengthy signal path conductors to the programmable elements. This often results in incomplete or ineffective programming, since the application of a specified programming voltage or current may not be sufficient to cause the corresponding programmable element so change state.
System-on-chip (SOC) products use fuses and PROMs to program functionality, enable redundancy, or for product identification and serialization. It is expected that three-dimensional (3D) products will have increased need for product customization and/or redundancy/repair schemes, with an accompanying high price in I/O requirements.
What is needed, therefore, is a structure and method by which device programming can be achieved that can reliably program programmable elements on a chip and which enables the use of fewer bonding pads.